Increasing instruction-level parallelism is regaining attractiveness within the microprocessor industry. The EOLE microarchitecture and D-VTAGE value predictor were recently introduced to solve practical issues of value prediction (VP). In particular, they remove the most significant difficulties that forbade an effective VP hardware. In this study, we present a detailed evaluation of the potential of VP in the context of EOLE/D-VTAGE and different compiler options. Our study shows that if no single general rule always applies—more optimization might sometimes leads to more performance—unoptimized codes often gets a large benefit from the prediction of redundant loads.