40nm SONOS Embedded Select in Trench Memory
Résumé
In this paper, we discuss a new development of
40nm SONOS eSTM™ (embedded Select in Trench Memory).
We present an experimental study based on hot carrier injection
mechanism for both programming/erase operations, performed
on this new eNVM architecture. The optimization of drain and
select gate biases, in order to define the programming and
erasing threshold voltages, is also detailed. All the
characterizations have been carried out for two different
SONOS eSTM™ architectures giving an opportunity to propose
different solutions. One of this using a continuous silicon nitride
layer for two neighbour cells, taking advantage on the discrete
charge trapping nature. As well, we performed endurance tests
up to one million cycles for both architectures to evaluate the
memory endurance.
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