This short-course surveys the status of recent research works in the domain of single event effects (SEE) in advanced CMOS technologies, such as fully depleted silicon-on-insulator (FD-SOI), FinFET, tri-gate or multi-gate configurations based on ultra-thin films or nanowire channels. This review primarily focus on the understanding of evolving risks related to SEE in such a "More Moore" roadmapping effort, mainly driven by an extreme geometrical scaling of devices and a concomitant supply voltage reduction. Some important key-points are particularly presented and discussed: the critical charge and ion-track spatial structure vs. device feature sizes, the impact of variability on SEE, the increasing sensitivity to background radiation (including the emerging issues of terrestrial muons and alpha-particles from traces of contaminants in device, circuit and packaging materials), the emergence of new physical mechanisms in advanced technologies (e.g. bipolar amplification). Finally, the review briefly discusses the SEE sensitivity of a few "More than Moore" CMOS solutions envisaged for 3D integration of future circuits.